wafer.space Community - 10G serdes tx/rx might work if we can go

10:07 a.m.

a thread!

The Tx to Rx path is currently a 3-tap CML TX, T-coil/midpoint ESD pad, differential channel, then dual-stage CTLE, VGA and separate data/monitor slicers. EQ adaptation uses shadow tuning codes allowing for simulated 1cm to 30cm “cable”. the monitor slicer measures eye/BER, the firmware qualifies a new code, then atomically swaps or rolls back, so the live data slicer is not disturbed while tuning.

djsftree

The Tx to Rx path is currently a 3-tap CML TX, T-coil/midpoint ESD pad, differential channel, then dual-stage CTLE, VGA and separate data/monitor slicers. EQ adaptation uses shadow tuning codes allowing for simulated 1cm to 30cm “cable”. the monitor slicer measures eye/BER, the firmware qualifies a new code, then atomically swaps or rolls back, so the live data slicer is not disturbed while tuning.

How do you make a non-interleaved gf180mcuD slicer fast enough for 10GBaud???

1:54 a.m.

I mean I think it's realistic with aggressive biasing plus fairly high Q inductive loading on it, using some transformer tactics to make something that can be rapidly reset/precharged back to neutral, but you didn't mention any such and even then I'm not actually convinced it's practical to do so....

I want it to be, because if you get that on this slow node, the same tricks should let us pull off PAM4 32GBaud (PCIe 6.0) on IHP SG13CMOS5L, even if not at full reach but mandating a redriver (with integrated DFE; as close as would be reasonable to route and with no connectors between the ASIC and the redriver) isn't excessive at that point... Which I do not think is reasonable to be on the table, unless it's literally the DFE that locks these fast transports from these affordable-MPW nodes.